1. Field of the Invention
The current invention generally relates to semiconductor products. More specifically, the present invention relates to making electrical resistance measurements that allow accurate measurement of the width of polysilicon conductors used in making FET (field effect transistor) gates in a FinFET semiconductor process.
2. Description of the Related Art
Field Effect Transistors (FETs) have been the dominant semiconductor technology used to make Application Specific Integrated Circuit (ASIC) chips, microprocessor chips, Static Random Access Memory (SRAM) chips, and the like for many years. In particular, Complementary Metal Oxide Semiconductor (CMOS) technology has dominated the semiconductor process industry for a number of years.
Technology advances have scaled FETs on semiconductor chips to increasingly small dimensions, allowing power per logic gate to be dramatically reduced, and further allowing a very large number of FETs to be fabricated on a single semiconductor chip. Scaling of FETs is currently running into limits. Gate oxides have become thin enough that leakage occurs through the gate oxides. Further scaling of gate oxide thickness will bring an exponential increase in leakage. Power dissipated by leakage currents has become a significant portion of total chip power, and an exponential increase in leakage results in unacceptable power dissipation for many types of chips.
Silicon on Insulator (SOI) processes have reduced FET source and drain capacitances, resulting in an improved power/performance ratio for CMOS chips fabricated in an SOI process. However, conventional SOI processes are reaching fundamental limits, resulting in undesirable effects such as the leakage effects mentioned above. Therefore, innovative new ways to make CMOS devices are being created. Associated apparatus and methods are also needed to test the innovative devices at various steps in the process of making them.
A conventional SOI FET is shown in FIG. 1A. A P− substrate 3 is provided. A buried oxide (BOX) 2 is created in the P− substrate using means such as oxygen implanting. Circuit elements are formed in a silicon layer above buried oxide 2, for example forming source 5, drain 6, and body 7. Source 5 and drain 6 are doped N+ for N channel Field Effect Transistors (NFETs) and P+ for P channel Field Effect Transistors (PFETs). Body 7 is typically P− doped for NFETs and N− doped for PFETs. Oxide 4 is a thin dielectric layer of oxide (or other suitable material). Gate 8 is typically formed of polysilicon. A wide variety of process techniques are used to improve such conventional FETs. For example, often the polysilicon gate 8, source 5, and drain 6 have silicide formed on them to enhance conductivity. Fundamentally, however, the polysilicon gate is planar and maintains a substantially uniform thickness and width throughout a length of the polysilicon shape of the gate. This uniform thickness and width of the polysilicon shape allows easy determination of the actual width of the gate on a semiconductor chip. Since the polysilicon width serves as a mask when implanting source/drain regions such as source 5 and drain 6, the polysilicon width determines the effective length of the FET produced by the polysilicon width. Process engineers find it useful to place a test structure on a semiconductor chip that allows easy determination of the particular polysilicon width (effective length of the FET) that can be used at various stages in the processing of the semiconductor chip.
FIG. 1B shows a prior art figure of a structure often placed on a semiconductor chip that allows easy determination of the width of a particular polysilicon conductor in a particular chip as fabricated. Note that polysilicon conductor width, like any process parameter, varies from one batch of semiconductor chips being made to another. Polysilicon conductor 12 is used to make a first resistor RA having a first contact 11A and a second contact 11B. Polysilicon conductor 12 is further used to make a second resistor RB, having a first contact 11B and a second contact 11C. Contact 11B is conveniently used for both the second contact of Resistor RA and the first contact of resistor RB in the example structure. Resistor RB comprises one or more fingers 13, each designed to be Leff units wide (arbitrary units). Leff is used to denote a desired channel length for FETs on the semiconductor chip. Other choices than the desired channel lengths for FETs on the semiconductor chip are possible, but typically the channel length is used. Polysilicon conductor width is the primary determinant of FET channel lengths on a semiconductor chip.
Resistor RA is simply a rectangle of polysilicon having a width “W” and a length “L”. The Sheet resistance of polysilicon conductor 12 is Rs ohms/square. Therefore,RA=Rs*L/W  (1)
Similarly, resistor RB is designed with a length of L (other lengths are possible, but L is a convenient dimension for resistor RB as well as resistor RA. Resistor RB, in the illustrative FIG. 1B is shown to have six fingers 13 connected in parallel, each having a width of “Leff”. Therefore,RB=⅙*Rs*L/Leff  (2)
Rs is “unknown” (without measurement of further test structures to determine the sheet resistivity of the polysilicon), but is the same for both resistors RA and RB on any particular semiconductor chip. Resistors RA and RB are readily measured for resistance values by suitable resistance measurements through contacts 11A, 11B, and 11C.Rs=RA*W/L (rearranging (1))  (3)Leff=Rs*L/(6*RB); (rearranging (2)); then, using Rs from (3) in (4),  (4)Leff=RA*W/(6*RB)  (5)
Note that the use of L1 for both resistors RA and RB conveniently eliminated L in the final equation. W still remains, and varies slightly from semiconductor chip to another semiconductor chip due to process variations, but W is made large enough that the process variations in W for a particular chip will have an insignificant effect on the determination of Leff.
Although only six fingers 13 are shown in FIG. 1B, such test structures have been constructed with differing (and usually many more than six) numbers of fingers 13.
The test structure and method of Leff determination described work very well when the polysilicon line has a substantially constant thickness.
Prior art FIGS. 2A and 2B show isometric views of a FinFET. A tall, thin fin 20 (referenced in FIG. 2B) of silicon material suitable for doping as source and drain regions rises from an oxide 19. Polysilicon gate 18 is a polysilicon conductor that surrounds fin 20 on three sides. In regions where the silicon material is doped P−, source 15 and drain 16 are subsequently doped to become N+ regions, with the P− region under gate 18 serving as a body 17 of the FinFET (body 17 shown in FIG. 2B). A thin gate oxide 14 separates polysilicon gate 18 from body 17. FinFETs have significant advantages, being “three dimensional” FETs, the gate can induce conducting channels on three sides, increasing current flow through a conducting FET, and making it less necessary that the gate oxide 14 be as thin as gate oxide 4 shown in FIG. 1A.
FIG. 2C shows an illustrative side view of polysilicon gate 18 as it goes over the tall, thin fin 20 at body 17. Although the polysilicon gate 18 has a thickness T1 when over a relatively wide region of oxide 19, gate 18 is much thinner at T2 and T3. The nonuniform thickness of polysilicon gate 18 as it goes over the “fins” renders the prior art test structure and method described above relatively ineffective in determining a channel length of a FinFET.
Therefore, there is a need for a method and apparatus that allow easy and accurate determination of channel length of a FinFET using resistance measurements.